`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:39:02 06/30/2015 
// Design Name: 
// Module Name:    Etapa1 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Etapa1(
	input PCSrc,
	input clk,
	input reset,
	input [31:0] jmpAddr,
	input jmp,
	input stallone,
	input [31:0] BranchData,
	output [31:0] Instruccion,
	output [31:0] E1Adder,
	output [31:0] PcOutsider,
	input enable
    );

wire [31:0] salidaPC;
wire [31:0] salidaMux;
wire [31:0] adder;
wire [31:0] salidaMux2;
wire [31:0] salidaMux3;
wire enalone;


assign adder = salidaPC + 4;
assign E1Adder = adder;
assign enalone = enable | stallone;
assign PcOutsider = salidaPC;
 
MemoriaInstrucciones MemIns(
.clk(clk),
.InstAddr(salidaPC),
.Inst(Instruccion));

PC ProgramC(
.clk(clk),
.reset(reset),
.d(salidaMux3),
.q(salidaPC));

Mux2to1 Mux(
.Input1(adder),
.Input2(BranchData),
.sel(PCSrc),
.Out(salidaMux));

Mux2to1 Mux2(
.Input1(salidaMux),
.Input2(jmpAddr),
.sel(jmp),
.Out(salidaMux2));

Mux2to1 MuxPC(
.Input1(salidaMux2),
.Input2(salidaPC),
.sel(enalone),
.Out(salidaMux3));


endmodule
